Abstract
Binary morphological operations are a building block in many computer vision applications. Several iterative morphological operations are commonly performed for image analysis resulting in a significant computational load on the processing unit, especially in a real-time computer vision system. Custom designed hardware can exploit the parallelism exhibited in binary image morphological operations. In this paper, we describe a scalable parallel Binary Morphological Unit (spBMU) which can produce 2×8-pixel (2 rows × 8 columns) outputs from one of fifteen primitive morphological operations based on a 3×3 mask. Multiple spBMU can be linked to achieve higher parallel performance. Operations include Sobel edge detection, dilation, erosion, Laplacian, and edge thinning. Implementation on an Altera CPLD has shown a sustained performance up to 720 million output pixels per second per chip at 45 MHz. Eight spBMUs, yielding 5.76 Giga-pixels/s, can be implemented with relatively small modification to the memory structure. The spBMU architecture and details of implementation are presented.
| Original language | English |
|---|---|
| Pages (from-to) | II444-II447 |
| Journal | Proceedings - IEEE International Symposium on Circuits and Systems |
| Volume | 2 |
| Publication status | Published - 2003 |
| Externally published | Yes |
| Event | Proceedings of the 2003 IEEE International Symposium on Circuits and Systems - Bangkok, Thailand Duration: 25 May 2003 → 28 May 2003 |
Keywords
- Binary morphological operations
- Image processing
- Programmable logic
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