Experimental Validation of a Phase Lead-Lag Synchronous Frame Phase-Locked Loop Under Different Voltage Conditions

Due to the rapid increase in single-phase inverters tied to the grid, fast and robust phase-locked loop algorithms have become indispensable. In previous work, a phase lead-lag synchronous reference frame phase-locked loop (PLL) was proposed. The method makes use of two single-tuned filters that perform as a phase detector. They are capable of shifting the phase of the grid voltage to be advanced or delayed by 45° with respect to the grid voltage phase. The generated orthogonal signals are transformed by Park transformation. The quadrature voltage is regulated to zero by means of a PI controller, while its output determines the frequency of the grid voltage and the phase angle obtained by integrating the estimated frequency. In this paper, deficiencies in the previous work are addressed. A small signal model of the method which takes into account frequency variation, voltage variation, and harmonic distortion is derived and presented. The design guidelines are discussed and an example illustrated. The method is validated through simulations and experiments under various voltage conditions while the algorithm is implemented on a rapid prototyping MicroLabBox. It is tested under different voltage scenarios, generated by a programmable AC source. The experimental results show that the method can track the phase angle of the grid voltage with nearly zero phase error under normal voltage conditions. It can track the phase of the grid voltage under 45° step phase jumps in 2.75 cycles, achieve harmonic attenuation of -15 dB under 15% third harmonic distortion, and attain an adequate phase margin near 45°. This confirms that the method is fast and robust under adverse voltage conditions.