A PROGRAMMABLE LOGIC-BASED IMPLEMENTATION OF ULTRA-FAST PARALLEL BINARY IMAGE MORPHOLOGICAL OPERATIONS

Songpol Ongwattanakul; Phaisit Chewputtanagul; David J. Jackson; Kenneth G. Ricks

A PROGRAMMABLE LOGIC-BASED IMPLEMENTATION OF ULTRA-FAST PARALLEL BINARY IMAGE MORPHOLOGICAL OPERATIONS

Songpol Ongwattanakul
, Phaisit Chewputtanagul
, David J. Jackson
, Kenneth G. Ricks

The University of Alabama

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

Binary morphological operations are a building block in many computer vision applications. Several iterative morphological operations are commonly performed for image analysis resulting in a significant computational load on the processing unit, especially in a real-time computer vision system. Custom designed hardware can exploit the natural parallelism exhibited in binary image morphological operations. In this paper we describe a parallel Binary Morphological Unit (pBMU) which can produce two 8-pixel outputs from one of fifteen morphological operations based on a 3x3 mask. Operations include Sobel edge detection, dilation, erosion, Laplacian, and edge thinning. Implementation on an Altera EPM7256SRC208-7 has shown a sustained performance of 1.066 billion output pixels per second at 66.67 MHz. Thus the pBMU can process 1,356 frame-operations on 1024x768 binary images every second. The pBMU architecture and details of implementation are presented.

Original language	English
Title of host publication	18th International Conference on Computers and Their Applications 2003, CATA 2003
Editors	Narayan C. Debnath
Publisher	The International Society for Computers and Their Applications (ISCA)
Pages	333-338
Number of pages	6
ISBN (Electronic)	9781618395498
Publication status	Published - 2003
Externally published	Yes
Event	18th International Conference on Computers and Their Applications, CATA 2003 - Honolulu, United States Duration: 26 Mar 2003 → 28 Mar 2003

Publication series

Name	18th International Conference on Computers and Their Applications 2003, CATA 2003

Conference

Conference	18th International Conference on Computers and Their Applications, CATA 2003
Country/Territory	United States
City	Honolulu
Period	26/03/03 → 28/03/03

Keywords

binary morphological operations
image processing
programmable logic

Cite this

Ongwattanakul, S., Chewputtanagul, P., Jackson, D. J., & Ricks, K. G. (2003). A PROGRAMMABLE LOGIC-BASED IMPLEMENTATION OF ULTRA-FAST PARALLEL BINARY IMAGE MORPHOLOGICAL OPERATIONS. In N. C. Debnath (Ed.), 18th International Conference on Computers and Their Applications 2003, CATA 2003 (pp. 333-338). (18th International Conference on Computers and Their Applications 2003, CATA 2003). The International Society for Computers and Their Applications (ISCA).

Ongwattanakul, Songpol ; Chewputtanagul, Phaisit ; Jackson, David J. et al. / A PROGRAMMABLE LOGIC-BASED IMPLEMENTATION OF ULTRA-FAST PARALLEL BINARY IMAGE MORPHOLOGICAL OPERATIONS. 18th International Conference on Computers and Their Applications 2003, CATA 2003. editor / Narayan C. Debnath. The International Society for Computers and Their Applications (ISCA), 2003. pp. 333-338 (18th International Conference on Computers and Their Applications 2003, CATA 2003).

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title = "A PROGRAMMABLE LOGIC-BASED IMPLEMENTATION OF ULTRA-FAST PARALLEL BINARY IMAGE MORPHOLOGICAL OPERATIONS",

abstract = "Binary morphological operations are a building block in many computer vision applications. Several iterative morphological operations are commonly performed for image analysis resulting in a significant computational load on the processing unit, especially in a real-time computer vision system. Custom designed hardware can exploit the natural parallelism exhibited in binary image morphological operations. In this paper we describe a parallel Binary Morphological Unit (pBMU) which can produce two 8-pixel outputs from one of fifteen morphological operations based on a 3x3 mask. Operations include Sobel edge detection, dilation, erosion, Laplacian, and edge thinning. Implementation on an Altera EPM7256SRC208-7 has shown a sustained performance of 1.066 billion output pixels per second at 66.67 MHz. Thus the pBMU can process 1,356 frame-operations on 1024x768 binary images every second. The pBMU architecture and details of implementation are presented.",

keywords = "binary morphological operations, image processing, programmable logic",

author = "Songpol Ongwattanakul and Phaisit Chewputtanagul and Jackson, \{David J.\} and Ricks, \{Kenneth G.\}",

note = "Publisher Copyright: {\textcopyright} 18th International Conference on Computers and Their Applications 2003, CATA 2003. All rights reserved.; 18th International Conference on Computers and Their Applications, CATA 2003 ; Conference date: 26-03-2003 Through 28-03-2003",

year = "2003",

language = "English",

series = "18th International Conference on Computers and Their Applications 2003, CATA 2003",

publisher = "The International Society for Computers and Their Applications (ISCA)",

pages = "333--338",

editor = "Debnath, \{Narayan C.\}",

booktitle = "18th International Conference on Computers and Their Applications 2003, CATA 2003",

}

Ongwattanakul, S, Chewputtanagul, P, Jackson, DJ & Ricks, KG 2003, A PROGRAMMABLE LOGIC-BASED IMPLEMENTATION OF ULTRA-FAST PARALLEL BINARY IMAGE MORPHOLOGICAL OPERATIONS. in NC Debnath (ed.), 18th International Conference on Computers and Their Applications 2003, CATA 2003. 18th International Conference on Computers and Their Applications 2003, CATA 2003, The International Society for Computers and Their Applications (ISCA), pp. 333-338, 18th International Conference on Computers and Their Applications, CATA 2003, Honolulu, United States, 26/03/03.

A PROGRAMMABLE LOGIC-BASED IMPLEMENTATION OF ULTRA-FAST PARALLEL BINARY IMAGE MORPHOLOGICAL OPERATIONS. / Ongwattanakul, Songpol; Chewputtanagul, Phaisit; Jackson, David J. et al.
18th International Conference on Computers and Their Applications 2003, CATA 2003. ed. / Narayan C. Debnath. The International Society for Computers and Their Applications (ISCA), 2003. p. 333-338 (18th International Conference on Computers and Their Applications 2003, CATA 2003).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Jackson, David J.

AU - Ricks, Kenneth G.

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N2 - Binary morphological operations are a building block in many computer vision applications. Several iterative morphological operations are commonly performed for image analysis resulting in a significant computational load on the processing unit, especially in a real-time computer vision system. Custom designed hardware can exploit the natural parallelism exhibited in binary image morphological operations. In this paper we describe a parallel Binary Morphological Unit (pBMU) which can produce two 8-pixel outputs from one of fifteen morphological operations based on a 3x3 mask. Operations include Sobel edge detection, dilation, erosion, Laplacian, and edge thinning. Implementation on an Altera EPM7256SRC208-7 has shown a sustained performance of 1.066 billion output pixels per second at 66.67 MHz. Thus the pBMU can process 1,356 frame-operations on 1024x768 binary images every second. The pBMU architecture and details of implementation are presented.

AB - Binary morphological operations are a building block in many computer vision applications. Several iterative morphological operations are commonly performed for image analysis resulting in a significant computational load on the processing unit, especially in a real-time computer vision system. Custom designed hardware can exploit the natural parallelism exhibited in binary image morphological operations. In this paper we describe a parallel Binary Morphological Unit (pBMU) which can produce two 8-pixel outputs from one of fifteen morphological operations based on a 3x3 mask. Operations include Sobel edge detection, dilation, erosion, Laplacian, and edge thinning. Implementation on an Altera EPM7256SRC208-7 has shown a sustained performance of 1.066 billion output pixels per second at 66.67 MHz. Thus the pBMU can process 1,356 frame-operations on 1024x768 binary images every second. The pBMU architecture and details of implementation are presented.

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BT - 18th International Conference on Computers and Their Applications 2003, CATA 2003

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Ongwattanakul S, Chewputtanagul P, Jackson DJ, Ricks KG. A PROGRAMMABLE LOGIC-BASED IMPLEMENTATION OF ULTRA-FAST PARALLEL BINARY IMAGE MORPHOLOGICAL OPERATIONS. In Debnath NC, editor, 18th International Conference on Computers and Their Applications 2003, CATA 2003. The International Society for Computers and Their Applications (ISCA). 2003. p. 333-338. (18th International Conference on Computers and Their Applications 2003, CATA 2003).

A PROGRAMMABLE LOGIC-BASED IMPLEMENTATION OF ULTRA-FAST PARALLEL BINARY IMAGE MORPHOLOGICAL OPERATIONS

Abstract

Publication series

Conference

Keywords

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