A Phase Lead-Lag Synchronous Reference Frame Phase-locked loop for Grid Synchronization of a Single-Phase Inverter

In this study, a phase lead-lag synchronous reference frame phase-locked loop (SRF-PLL) is proposed for the grid connection of a single-phase inverter. A tuned filter is employed to enable the phase of the input voltage to be advanced or delayed by ±45 degrees with respect to the grid voltage. The generated orthogonal signals are fed into Park’s transformation. Only the quadrature-phase signal is regulated to zero using a PI controller. Its output determines the estimated frequency. The phase angle is obtained by integrating the estimated frequency. The linearized model of the proposed SRF-PLL is developed and stability analysis is discussed. The viability of the proposed method is tested under computer simulation using MATLAB/Simulink. The method is then implemented on a 32-bit microcontroller and tested with a programmable AC source. The results positively confirm the effectiveness of the method.