A 1 GHz CMOS analog equalizer for perpendicular magnetic recording

Sukarasut Meksiri; Kasin Vichienchom; Decha Wilairat

doi:10.1109/TENCON.2010.5686144

A 1 GHz CMOS analog equalizer for perpendicular magnetic recording

Sukarasut Meksiri
, Kasin Vichienchom
, Decha Wilairat

Department of Electrical Engineering

King Mongkut's Institute of Technology Ladkrabang

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Citations (Scopus)

Abstract

This paper describes the design of a CMOS analog discrete-time equalizer for perpendicular magnetic recording (PMR) read channel. In this design the structure of analog FIR filter that places rotating switch matrix between DAC and multiplier has been proposed. It reduces an accumulative switching error in analog samples due to rotating switch matrix. A 7-tap filter circuit based on GPR2 target was designed and simulated using TSMC 0.18 μm CMOS process parameters. Simulation results show good agreement with the results of the system level simulation. At 1 GHz sampling frequency the equalizer dissipates 1.5 mW.

Original language	English
Title of host publication	TENCON 2010 - 2010 IEEE Region 10 Conference
Pages	1521-1524
Number of pages	4
DOIs	https://doi.org/10.1109/TENCON.2010.5686144
Publication status	Published - 2010
Event	2010 IEEE Region 10 Conference, TENCON 2010 - Fukuoka, Japan Duration: 21 Nov 2010 → 24 Nov 2010

Publication series

Name	IEEE Region 10 Annual International Conference, Proceedings/TENCON

Conference

Conference	2010 IEEE Region 10 Conference, TENCON 2010
Country/Territory	Japan
City	Fukuoka
Period	21/11/10 → 24/11/10

Keywords

Analog signal processing
CMOS analog circuit
Discrete-time equalizer
FIR
Perpendicular magnetic recording

Access to Document

10.1109/TENCON.2010.5686144

Cite this

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title = "A 1 GHz CMOS analog equalizer for perpendicular magnetic recording",

abstract = "This paper describes the design of a CMOS analog discrete-time equalizer for perpendicular magnetic recording (PMR) read channel. In this design the structure of analog FIR filter that places rotating switch matrix between DAC and multiplier has been proposed. It reduces an accumulative switching error in analog samples due to rotating switch matrix. A 7-tap filter circuit based on GPR2 target was designed and simulated using TSMC 0.18 μm CMOS process parameters. Simulation results show good agreement with the results of the system level simulation. At 1 GHz sampling frequency the equalizer dissipates 1.5 mW.",

keywords = "Analog signal processing, CMOS analog circuit, Discrete-time equalizer, FIR, Perpendicular magnetic recording",

author = "Sukarasut Meksiri and Kasin Vichienchom and Decha Wilairat",

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doi = "10.1109/TENCON.2010.5686144",

language = "English",

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series = "IEEE Region 10 Annual International Conference, Proceedings/TENCON",

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Meksiri, S, Vichienchom, K & Wilairat, D 2010, A 1 GHz CMOS analog equalizer for perpendicular magnetic recording. in TENCON 2010 - 2010 IEEE Region 10 Conference., 5686144, IEEE Region 10 Annual International Conference, Proceedings/TENCON, pp. 1521-1524, 2010 IEEE Region 10 Conference, TENCON 2010, Fukuoka, Japan, 21/11/10. https://doi.org/10.1109/TENCON.2010.5686144

A 1 GHz CMOS analog equalizer for perpendicular magnetic recording. / Meksiri, Sukarasut; Vichienchom, Kasin; Wilairat, Decha.
TENCON 2010 - 2010 IEEE Region 10 Conference. 2010. p. 1521-1524 5686144 (IEEE Region 10 Annual International Conference, Proceedings/TENCON).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

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AU - Meksiri, Sukarasut

AU - Vichienchom, Kasin

AU - Wilairat, Decha

PY - 2010

Y1 - 2010

N2 - This paper describes the design of a CMOS analog discrete-time equalizer for perpendicular magnetic recording (PMR) read channel. In this design the structure of analog FIR filter that places rotating switch matrix between DAC and multiplier has been proposed. It reduces an accumulative switching error in analog samples due to rotating switch matrix. A 7-tap filter circuit based on GPR2 target was designed and simulated using TSMC 0.18 μm CMOS process parameters. Simulation results show good agreement with the results of the system level simulation. At 1 GHz sampling frequency the equalizer dissipates 1.5 mW.

AB - This paper describes the design of a CMOS analog discrete-time equalizer for perpendicular magnetic recording (PMR) read channel. In this design the structure of analog FIR filter that places rotating switch matrix between DAC and multiplier has been proposed. It reduces an accumulative switching error in analog samples due to rotating switch matrix. A 7-tap filter circuit based on GPR2 target was designed and simulated using TSMC 0.18 μm CMOS process parameters. Simulation results show good agreement with the results of the system level simulation. At 1 GHz sampling frequency the equalizer dissipates 1.5 mW.

KW - Analog signal processing

KW - CMOS analog circuit

KW - Discrete-time equalizer

KW - FIR

KW - Perpendicular magnetic recording

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DO - 10.1109/TENCON.2010.5686144

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Y2 - 21 November 2010 through 24 November 2010

ER -

A 1 GHz CMOS analog equalizer for perpendicular magnetic recording

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Keywords

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